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Logic synthesis
Results: 291

#	Item
161	Technology Mapping with Boolean Matching, Supergates and Choices Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-04-19 22:57:46 Logic synthesis Circuit Standard cell Boolean function Electronic engineering Electronic design automation And-inverter graph
162	Scalably-Verifiable Sequential Synthesis Robert Brayton Alan Mishchenko Department of EECS, University of California, Berkeley Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-10-02 14:31:33 Electronic design automation Digital electronics Logic in computer science Electrical circuits And-inverter graph Retiming Automatic test pattern generation Formal verification Combinational logic Electronic engineering Formal methods Theoretical computer science
163	Topologically Constrained Logic Synthesis Add to Reading List Source URL: www.bvsrc.org - Date: 2005-05-01 22:10:33
164	Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 02:15:25 Electronics Diagrams Boolean algebra And-inverter graph Circuit Logic synthesis Topology Boolean function Artificial neuron Electronic engineering Electromagnetism Electronic design automation
165	Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Jie-Hong Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-05-01 15:17:53 Digital electronics Electronic design And-inverter graph Retiming Logic synthesis Algorithm Field-programmable gate array Logic gate Parallel computing Electronic engineering Electronic design automation Formal methods
166	FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton Department of EECS, University of California, Berkeley {alanmi, satrajit, jiejiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-04-01 15:19:32 Boolean algebra Diagrams Digital electronics And-inverter graph Binary decision diagram Logic optimization Model checking Boolean function Logic synthesis Electronic engineering Electronic design automation Formal methods
167	An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 00:13:15 Integrated circuits Electronic design Placement Logic synthesis Field-programmable gate array Jason Cong Complex programmable logic device Application-specific integrated circuit Electronic engineering Electronics Electronic design automation
168	Scalable and Scalably-Verifiable Sequential Synthesis Alan Mishchenko Michael Case Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-07-28 20:26:28 Electronic design automation Electrical circuits And-inverter graph Diagrams Retiming Automatic test pattern generation Scan chain Combinational logic Sequential logic Electronic engineering Formal methods Digital electronics
169	Sequential Logic Synthesis Using Symbolic Bi-Decompsition Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-05-13 19:30:33 Electronic engineering Reed-Muller expansion Function Logic optimization Combinatory logic Canonical form Binary decision diagram Path decomposition Asynchronous logic Mathematics Mathematical logic Boolean algebra
170	SAT-Based Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-09-24 19:38:05 Electrical engineering Electronics And-inverter graph Boolean network Mathematical optimization Logic synthesis Lookup table Electronic engineering Electronic design automation Diagrams

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